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om AVS Technology .c 4U et he FEATURES aS 24/20-bit DACs. t * Six Channel adB SNR - 102 .D dB Dynamic Range. w104 w N w -- -92 dB THD +96 Ratio. 32,44.1, 48, and 192KHz. Sampling
AV2388
Multi-Channel Audio CODEC
48, 96 and 192KHz. Sampling Rates, 192 fs or 128 fs for 96 KHz Sampling Rates. and 86 fs or 64 fs for 192 KHz. Sampling Rate. * Automatic input format detection. * 5-volt Power Supply. * 3.3 -volt Digital Interface Friendly. * I2C Interface for Mode Setting. Applications
rates. - 24, 20, 18 and 16-bit Digital Inputs. - Containing Digital De-emphasis Filters. - Independent Digital Volume Control. - I2S, Left and Right Justified Digital Input Formats. - Auto-Mute Control. - On -chip Reconstruction Filters. - -96 dB THD + N Ratio. - I2S and Left Justified Output Formats. * System clock: 384 fs or 256 fs for 32, 44.1
SDA SCL
80 80 77
SD1 SD2 SD3
SF SC
77 78
m o .c U t4 e e h S ta a .D w w w
* 28 pin SOP package
I2C Serial Control Port
* Digital Surround Sound For Home Theater * DVD * Car Audio.
AV2388
D/A D/A
40KHz 40KHz 40KHz 40KHz 40KHz 40KHz
VOR3 VOL3
5th Order Modulators
Digital Volume
De-Emphasis
96 Times Over-sampling Filters
D/A
VOR2 VOL2 VOR1 VOL1
AVS Technology Inc. 4110 Clipper Ct., Fremont CA94538 Tel: (510) 353-0848 Fax: (510) 353-0856
Audio I/F
Format Detect'n
Serial
D/A D/A D/A
PLL
15
XCK
RST
1-20
om .c 4U et he aS at .D w w w
15
VCM
January 3, 2002
AV2388
Item
PERFORMANCE SPECIFICATIONS
Audio DAC
Spec.
1 2 3 4 6 7 8 9 10
Audio Output Level Audio Bandwidth 20Hz - 20 KHz SNR (A-weight, Muted) SNR (A-weight, Not Muted) THD + N (A-weight, FFS Output) Dynamic Range Channel Separation Nonlinear Distortion Channel Gain Error
1 Vrms +/- 0.1 dB >102 dB >96 dB < -92 dB 104 dB < -96 dB < 0.25 dB < 0.1 dB
All Measurement were taken with only one channel active.
2-20
January 3, 2002
AV2388 DESCRIPTION
The AV2388 is a mixed signal CMOS monolithic audio CODEC. It consists of six channels sigma delta DACs The DACs support 24, 20, 18 and 16-bit input data. It also support multiple sampling frequency data. Each DAC has it own individual volume control.
XCK REQUIREMENT
The AV2388 supports 384 and 256 times sampling clock for 32, 44.1, 48, 96 and 192K audio; 192 or 128 times for the 96 K audio.; and 96 and 64 times for the 192K audio.
XCK Requirement
Sampling Rate XCK Freq. PLLcntl=[0 0] Normal XCK 384*fs 32 K 44.1 48 K 96 K 192 K 12.288 MHz 16.934 Mhz 18.432 MHz 18.432 MHz 18.432 Mhz 256*fs 8.192 MHz 11.29 Mhz. 12.288 Mhz. 12.288 Mhz. 12.288 Mhz. PLLcntl=[1 0] 4 times XCK 4*384*fs 49.152 MHz 67.738 Mhz 73.728 MHz 73.728 MHz 73.728 Mhz 4*256*fs 32.768 MHz 45.158 Mhz. 49.152 Mhz. 49.152 Mhz. 49.152 Mhz. PLLcntl=[0 1] 2 times XCK 2*384*fs 24.576 MHz 33.869 Mhz 36.864 MHz 36.864 MHz 36.864 Mhz 2*256*fs 16.384 MHz 22.579 Mhz. 24.576 Mhz. 24.576 Mhz. 24.576 Mhz.
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January 3, 2002
AV2388 PIN ASSIGNMENT
SD3 SD2 SD1 TSTO SC SF DGND DVDD DGND XCK SCL SDA TST RST 1 2 3 4 5 28 27 26 25 24 AR1 AL1 AR2 AL2 AR3 AL3 AGND VCM AVDD N/C AGND N/C N/C N/C
AV2388
6 7 8 9 10 11 12 13 14
23 22 21 20 19 18 17 16 15
PIN DESCRIPTION
Pin Name DIGITAL SD3 SD2 SD1 TSTO SC SF 1 2 3 4 5 6 I I I O I I Audio Serial Data Input 3. Audio Serial Data Input 2. Audio Serial Data Input 1,.. Test output pin. This pin should be no be connected. Audio Serial Data Clock pin. Left/Right Channel Clock pin. For Left justified or Right justified mode, a high in SF indicates Left Channel Data, a low in SF indicates Right Channel Data. For I2S mode, a low in SF indicates Left Channel Data, a high in SF indicates Right Channel Data. Digital ground Digital power supply. Digital ground External Master Clock Input. Pin # Type Description
DGND DVDD DGND XCK
7 8 9 10
GND +5V GND I
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January 3, 2002
AV2388 PIN DESCRIPTION (Continued)
Pin Name SCL SDA TST RST Analog AR1 AL1 AR2 AL2 AR3 AL3 AVSS VCM AVDD N/C AGND N/C N/C N/C 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND I I +5V O O O O O O GND Analog right channel 1 output Analog left channel 1 output Analog right channel 2 output. Analog left channel 2 output. Analog right channel 1 output. Analog left channel 1 output. Analog circuits ground Common voltage output pin for the DAC. Analog circuits power supply No connection. Can be tied to AVSS Analog circuits ground No connection. Can be tied to AVSS No connection. Can be tied to AVSS No connection, Can be tied to AVSS Pin # 11 12 13 14 Type I I/O O I I2C clock input. I2C DATA bus. Open drain output. Externally this pin should tie to a 680 ohm pull up resistor. Test fs reference pin. For test vector verification. For normal operation this pin must be tied to `0'. Active low power down reset. When low, the chip is reset and all programmable registers are reset to default values. Description
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January 3, 2002
AV2388 DIGITAL AUDIO SERIAL INTERFACE
The digital serial interface consists of 3 serial input pins, SD1, SD2, SD3, and one serial clock input pin, SC, and one left/right indicator input pin, SF. The data are 2's complement MSB first numbers. The AV2388 supports four resolution, which are selected either by setting the FMT[1] and FMT[0] pins or by programming the control register CREG0[5:4] via the I2C serial control port. Table 1 describes these four resolution.
Table (1): Audio Serial Data Input Format,
Format 0 1 2 3 CREG0[5] 0 0 1 1 CREG0[4] 0 1 0 1 SD1, SD2, and SD3 24-bit 20-bit 18-bit 16-bit
The SD3, SD2 and SD1 can be either 24-bit or 32-bit per frame as well as left justified, right justified or I2S. The AV2388 counts the number of BCK per frame to determine whether the input is 24 or 32 bits format.
Table (1): Audio Serial Data Input Modes
Mode 0 1 2 3 CREG0[7] 0 0 1 1 0REG0[6] 0 1 0 1 SD1, SD2, and SD3 Right Justified I2S Left Justified Invalid
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January 3, 2002
AV2388 Figure 1. Audio Serial Input Data Timing Diagram
1/fs
SF SC MSB SD1,2,3
LEFT CHANNEL
RIGHT CHANNEL
LSB
2 1 0
MSB
2 1
LSB
0
Right justified, CREG0[7,6]=[0 0] LEFT CHANNEL 1/fs RIGHT CHANNEL
SF SC MSB SD1,2,3
LSB
0
MSB
1
LSB
0
Left justified, CREG0[7,6]=[1 0] 1/fs
LEFT CHANNEL SF SC MSB SD1,2,3
1 0
RIGHT CHANNEL
LSB
MSB
1
LSB
0
IIS, CREG0[7,6]=[0 1]
Figure 2.
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January 3, 2002
AV2388 Figure 3. Audio Serial Output Data Timing Diagram
1/fs
SF SC MSB SD1,2,3
23 22 21
LEFT CHANNEL
RIGHT CHANNEL
LSB
2 1 0
MSB
23 22 21 2 1 0
LSB
Left justified, CREG0[7,6]=[X 0]
LEFT CHANNEL SF SC SD1,2,3 MSB
23 22 21 2
1/fs
RIGHT CHANNEL
LSB
1 0
MSB
23 22 21 2
LSB
1 0
IIS, CREG0[7,6]=[0 1]
8-20
January 3, 2002
AV2388 INFINITE ZERO DETECTION
The AV2388 has an Infinite Zero Detection circuit which detects zero in the Audio Serial Port that lasts for approximately 0.5 sec. By default, the zero detection circuit is on.
Serial Command Port
The user can use the pin to select the chip operation or by programming the internal control registers through the 7 bit address I2C port. The Chip Address for the AV2388 is 31H. The protocol for write operation consists of sending 3 byte data to AV2388, following each byte are the acknowledges generated by AV2388. The first byte is the 7-bit Chip Address followed by the read/write bit (read is high write is low). The second byte is the control register address. The third byte is the control register data. Upon power up, all programmable registers are set to default values. Figure 4 describes the serial command port timing relationship.
Figure 4. Serial Command Port Timing
I2 C Bus Control Register write example:
Start
CA6
CA0 R/W ACK A7
A0
ACK D7
D0 ACK
Stop
SDA
1
1
1
SCL
Chip adrress: CA<6:0> = 31H Register address: A<7:0> = 00H DATA: D<7:0> = 30H
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January 3, 2002
AV2388 SERIAL PORT CONTROL REGISTER ASSIGNMENT
There are 10 registers dedicated to the AV2388 for chip functional programming,. One register for testing. The register addresses assignments are
Address (decimal) 0 1 2 3 4 5 6 7 8 9
Register CREG0[7:0] CREG1[7:0] VOLREG0[7:0] VOLREG1[7:0] VOLREG2[7:0] VOLREG3[7:0] VOLREG4[7:0] VOLREG5[7:0] MUTE[5:0] TREG1[7:0]
Default Value 80 80 80 80 80 80 80 80 00 00
Register Function Data input format, de-emphasis filter selection Input format and PLL output frequency selection Volume control for channel 1, left Volume control for channel 1, right Volume control for channel 2, left Volume control for channel 2, right Volume control for channel 3, left Volume control for channel 3, right Mute control register. Test control
10-20
January 3, 2002
AV2388 CONTROL REGISTERS DESCRIPTION
Control Register 0(ADRS=hex00, default=hex80)
CREG0[7:0] ADDR[4:0] BIT 7 Hex 00 Default Value R/W
LT
BIT 6 IIS 0 R/W
BIT 5
BIT 4
BIT 3 AMUTE
BIT 2 AMPX2 0 R/W
BIT 1
BIT 0
FMT[1:0] 0 R/W 0 R/W
FIRSL[1:0] 0 R/W 0 R/W
1 R/W
0 R/W
[LT, IIS] Digital Serial Bus Format Select 00: - Normal or Right Justified Format. 01: - I2S Format. 10: - Left Justified Format. (default) 11: - Not allowed. FMT[1:0]: - These two bits define the serial audio input resolution 00: - 24-bit resolution. (default) 01: - 20-bit resolution. 10: - 18-bit resolution. 11: - 16-bit resolution. AMUTE: - Active low auto-mute detection enable. 0: - Auto-mute enabled. (default) 1: - No auto-mute. AMPX2: - Multiplied the Volume by two. 0: - Normal. (default) 1: - Volume is doubled. Should be used with Pre-De-emphasis track. DEML: - De-emphasis Control 00: - No De-emphasis. (default) 01: - Select 44.1K De-emphasis filter. 10:- Select 48 K De-emphasis filter. 11: - Select 44.1K and 36K sampling filter: No De-emphasis.
Control Register 1 (ADRS=hex01, default=hex80)
CREG1[7:0] ADDR[4:0] BIT 7 Hex 01 Default Value R/W Autodet 1 R/W BIT 6 zero 0 R/W BIT 5 fs384 0 R/W BIT 4 px4s 0 R/W BIT 3 px2s BIT 2 zero 0 R/W BIT 1 PLLcntl1 0 R/W BIT 0 PLLcntl0 0 R/W
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January 3, 2002
AV2388
Autodet: Input format auto detection enable 0 - disable input format detection. The user need to program bit[5:3] in order to select the input format and filters for 96K and 192K sampling. 1 - enable input format detection. F384: XCK frequency. 0 -XCK is 384 times the bit clock, SCK. 1 - XCK is 256 times the bit clock, SCK. [Px4s Px2s]: Higher sampling filter selection. [0 0] - normal sampling. [0 1] - 2 times over sampling filter enable. [1 0] - 4 times over sampling filter enable. [1 1] - invalid. PLLcntl[1:0]:System clock PLL control. [ 0 0] - normal sampling XCK input. [ 0 1] - 2 times XCK input. [ 1 0] - 4 times XCK input. [ 1 1] - invalid
Volume Registers for channel 1 to channel 3, (ADRS=hex02 - hex07, default=hex80)
Volume Registers ADDR[4:0] BIT 7 Hex 02 Hex 03 Hex 04 Hex 05 Hex 06 Hex 07 Default Value BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Channel 1 left volume register, VLREG0L[7:0] Channel 1 right volume register, VLREG0R[7:0] Channel 2 left volume register, VLREG1L[7:0] Channel 2 right volume register, VLREG!1R[7:0] Channel 3 left volume register, VLREG2L[7:0] Channel 3 right volume register, VLREG2RL[7:0] 1 0 0 0 0 0 0 0
VOLREG:- Control the volume of the 6 DAC's 80h- corresponds to 0 dB setting. Value should not be programed greater than 80h.
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January 3, 2002
AV2388 Mute Reg (ADRS=hex10, default=hex80)
Mute[5:0] ADDR[4:0] BIT 7 Hex 01 Default Value R/W R/W 0 BIT 6 BIT 5 Mute3R 0 R/W BIT 4 Mute3L 0 R/W BIT 3 Mute2R BIT 2 Mute2L 0 R/W BIT 1 Mute1R 0 R/W BIT 0 Mute1L 0 R/W
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January 3, 2002
AV2388 Application Connection Example:
Digital
4.7 ohm
Analog +5 Volt
20 AVCC
22 uF
8 DVCC 1 SD3 2 SD2
22 uF
28 AR1 27
22 uF
Digital Audio Interface
3 SD1 5 SC 6 SF 10 XCK
22 uF 22 uF 22 uF 22 uF 22 uF
AL1 26 AR2 25 AL2 AR3 AL3 24 23
Over Sample Clock
+5 Volt 680 ohm
11 I C Serial Interface
2
AV2388
SCL 12 SDA
21
VCM
4.7uF
13 TST 14
Reset
RST DVSS AVSS 15 18 22
All Unmarked Capacitors are 0.1 uF
7
9
14-20
January 3, 2002
AV2388 TIMING DIAGRAM Figure 5. Audio Serial Interface Timing Requirement
tsc tscH tscL
SC
tsd su
SD1-3
tsdout mx tsd hd
SDOUT
tsf su tsdout mn
SF
tsf hd
Figure 6. Serial Command Port Write Timing Requirement
tBUF tSU;STA
SDA
tHD;STA tHIGH tSU;DAT tSU;STO
SCL
P
S
tLOW tR tF tHD;DAT
Sr
P
15-20
January 3, 2002
AV2388 Figure 7. Power Down / Reset Timing
trst PWD
ABSOLUTE MAXIMUM RATINGS
Symbol VDD Vi Ai Vo Ao TDsc TASC Ta Tstg Tj Tsol Tvsol Tstor Notes:
Characteristics Power Supply Voltage (Measured to GND) Digital Input Applied Voltage2 Digital Input Forced Current3,4 Digital Output Applied Voltage2 Digital Output Forced Current3,4
Digital Short Circuit Duration (single output high state to Vss)
Min -0.5 GND-0.5 -100 GND-0.5 -100
Max +7.0
Units V V
100 VDD+0.5 100 1 infinite
mA V mA Sec Sec
o o o o o o
Analog Short Circuit Duration (single output to VSS1) Ambient Operating Temperature Range Storage Temperature Range Junction Temperature (Plastic Package) Lead Soldering Temperature (10 sec., 1/4" from pin) Vapor Phase Soldering (1 minute) Storage Temperature -65 -25 -65 -65
+125 +150 +150 300 220 +150
C C C C C C
1. Absolute maximum ratings are limiting values applied individually, while all other parameters are within specified operating conditions. 2. Applied voltage must be current limited to specified range, and measured with respect to VSS. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current, flowing into the device.
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January 3, 2002
AV2388 RECOMMENDED OPERATING CONDITIONS
Symbol VDD VVCM RL Ta
Characteristics Power supply voltage Reference voltage Analog output load Ambient operating temperature range
Min 4.5
Typical 5 2.25 37.5
Max 5.5 2.41 70 70
Units V V
o
0
C
ELECTRICAL CHRACTERISTICS
Parameter Supply IDD
Characteristics
Min
Typ
Max
Units
Total Power Supply Current, Analog + Digital
135
145
mA
Digital Characteristics VIH VIL IIH IIL CIN VOH VOL IOZH IOZL CI CO Digital Input Voltage, Logic HIGH, TTL Compatible Inputs. Digital Input Voltage, Logic LOW, TTL Compatible Inputs Digital Input Current, Logic HIGH, (VIN=4.0V) Digital Input Current, Logic LOW, (VIN=0.4V) Digital Input Capacitance (f=1Mhz, VIN=2.4V) Digital Output Voltage, Logic HIGH, (IOH= -1mA) Digital Output Voltage, Logic LOW, (IOL=4.0 mA) Hi-Z Leakage Current, HIGH, VDD=Max, VIN=VDD) Hi-Z Leakage Current, LOW, VDD=Max, VIN=VSS) Digital Input Capacitance (TA=25oC, f=1Mhz) Digital Output Capacitance (TA=25oC, f=1Mhz) 3.2 VSS 3.4 2.0 VSS VDD 0.8 10 -10 7 3.5 0.4 10 -10 8 10 V V
A A
pF V V
A A
pF pF
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January 3, 2002
AV2388
Parameter
Characteristics
Min
Typ
Max
Units
Audio Serial Interface Timing
tsc
SC Cycle Time SC Pulse Width, HIGH SC Pulse Width, LOW Audio Data Setup Time With Respect To Rising Edge of SC Audio Data Hold Time With Respect to Rising Edge of SC Audio SFSetup Time With Respect To Rising Edge of SC Audio SF Hold Time With Respect To Rising Edge of SC SC falling edge to SDOUT Valid SC falling edge to SDOUT Valid
80 30 30 10 15 10 15 25 5
ns ns ns ns ns ns ns ns ns
tscH tscL tsdsu tsdhd tsfsu tsfhd tsdoutmx tsdoutmn Reset Signal trst
Active low reset time
1
s
Serial Command Port
fsc tsu;sta thd;sta tsu;sto tLOW tHIGH tr tf tsu;DAT thd;DAT tvd;DAT tBUF
SCL Clock Frequency Start condition set up time Start condition hold time Stop condition set up time SCL Low time SCL High time SCL & SDA rise time SCL & SDA fall time Data set-up time Data hold time SCL LOW to data out valid Bus Free time 4.7 250 0 4.7 4.0 4.0 4.7 4.0
100
kHz us us us us us
1.0 0.3
us us ns ns
3.4
us us
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January 3, 2002
AV2388
Parameter Audio DAC Characteristics SNR THD+N
Characteristics
Min
Typ
Max
Units
Signal To Noise Ratio Total Harmonic Distortion + Noise Dynamic Range Channel Separation Full Scale Output Voltage Center Voltage Inter-channel Gain Mismatch Analog Output Load Resistance Analog Output Load Capacitance
99 94 102 84 .96 2.18
102
dB dB
104 97 1 2.20 0.1 1.02 2.25
dB dB Vrms V dB K 100 pF
5
19-20
January 3, 2002
AV2388 PACKAGING INFORMATION Dimensions
Mils min A A1 norm max min Mils norm max
93 4 14 9 691
100 8 16 10 702
104 12 19 12 713
E1 E2
291 394
295 406 50
299 419
b C
D
e
L
20
30
40
28-Pin (SOP)
D
E1
E2
A1
A
b
e c L
20-20
January 3, 2002

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